The present invention is directed to semiconductor devices, and more particularly to testing semiconductor memory devices for defects.
Defects in semiconductor integrated circuit memory devices, such as dynamic random access memory (DRAM) devices, are tested for during production at different stages. Defects in the devices that are detected after completed manufacturing and before integrated circuit packaging are “repaired” by the use of redundant elements. Defects that are detected after packaging lead to rejection of the device.
Currently, defects such as wordline-bitline short-circuits are detected by functional test patterns that compare expected data against actual data. If mismatches occur, the corresponding addresses are stored. A bitmap such as the one shown in FIG. 1 would be identified as a wordline-bitline short either by a redundancy algorithm or by bitmap analysis, and the bitmap shown in FIG. 2 might be recognized as a wordline-wordline short-circuit.
With current testing techniques, the ability to detect a defect depends on the nature of the resistive short. High resistive shorts reduce the signal margin only for the cells on the shorted bitline so that a bitline-oriented failure may be possibly detected. Such a testing technique is not reliable because only a secondary effect is measured. Furthermore, this approach makes defect localization very difficult and requires time consuming analysis techniques to localize a defective wordline because if only a bitline oriented defect is detected, it is not clear from which deactivated wordline the leakage originates.